As semiconductor device technology evolves, there is an ever-present need for shrinking all aspects of semiconductor device sizes. However, design and manufacture of various components of semiconductor devices involves different materials and processes, and accordingly, different components scale differently. For example, while sizes of logic and memory cells on a semiconductor chip shrink rapidly as they evolve into the low nanometer and sub-nanometer scales, it is very challenging to shrink the interconnections between these cells at comparable pace. The interconnections are predominantly made up of metal lines, typically formed by materials such as Copper (Cu). Decreasing the size, in terms of thickness or cross sectional area, of these metal lines leads to various issues.
More specifically, for short interconnections between on-chip logic and/or memory elements, it is preferable to use a metal line on a same layer as these elements in order to improve speed. Typically, such interconnections are formed on a so called first level, or level 1 or layer 1, and are generally referred to as metal 1 (M1) metal lines. Longer routing paths are formed in different layers, such as, levels 2, 3, 4, and beyond, and interconnections between these higher level metal lines (e.g., M2, M3, M4, etc.) involve the use of inter-level vias which introduce additional delay. Accordingly for local routing, for example, for short interconnections which are required to have a small critical path, M1 interconnections are preferred.
The delay introduced by a metal line is proportional to a product of resistance (R) and capacitance (C) of the metal line, and is usually referred to as a resistance-capacitance or “RC” delay. As the size of the metal line is reduced, both resistance and capacitance of the metal line increase. In the case of M1 metal lines, it seen that in order to reduce the RC delay of M1 metal lines, reducing the capacitance is more important than reducing the resistance, because increasing capacitance tends to have adverse effects on performance of nearby elements, such as neighboring M1 metal lines, logic, memory cells, etc.
Based on process parameters, reducing capacitance of M1 metal lines can be most effectively achieved by reducing the height of the M1 metal lines. However, naively reducing the metal height of M1 metal lines can lead to harmful side-effects. This is because reducing the metal height leads to a smaller cross-sectional area of the M1 metal line, which increases current density. A higher current density affects electromigration reliability. In general, electromigration tends to be a key reliability issue in Cu metallization. Briefly, the issue can be explained with respect to current flowing through a Cu metal line. When high current (or in other words, a large number of electrons) flows through Cu, the Cu atoms can move along with the movement of the electrons. As a result, a void or decrease of Cu atoms may occur in some portions of the Cu metal line, while a hill or increase of Cu atoms may occur in other portions of the Cu metal line, thus leading to failure or loss of reliability, for example in dielectric layers which may be formed adjacent to M1 metal lines formed from Cu in conventional designs.
In an effort to prevent such side-effects and preserve electromigration reliability, existing technology-specific design rules impose restrictions on the minimum size to which M1 metal lines can be shrunk. These rules are based on conventional M1 metal lines formed of Cu, and also take into account the limitations of Cu filling processes needed for forming the M1 metal lines. Accordingly, the conventional M1 metal lines formed from Cu cannot be safely shrunk below these predetermined minimum sizes, and thus, limits are imposed on the overall layout scaling of semiconductor devices. Due to these restrictions on the minimum sizes, the height of the M1 metal line cannot be reduced beyond these restrictive minimum sizes, and therefore, capacitance and RC delays tend to be undesirably high.